Cmos image sensor and method for fabricating the same

ABSTRACT

A CMOS image sensor includes a substrate, a gate electrode formed over the substrate, a photodiode formed over the substrate to be substantially aligned with one side of the gate electrode, a floating diffusion region formed over the substrate to be substantially aligned with the other side of the gate electrode, and a blooming pass region formed below the photodiode.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2012-0073964, filed on Jul. 6, 2012, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a semiconductordevice fabrication technology, and more particularly, to a complementarymetal-oxide semiconductor (CMOS) image sensor and a method forfabricating the same.

2. Description of the Related Art

A complementary metal-oxide semiconductor (CMOS) image sensor is anintegrated sensor having a block configured to amplify or process signalin a sensor chip using an active element such as a MOS or CMOStransistor.

In general, a unit pixel of the CMOS image sensor includes onephotodiode PD and four NMOS transistors TX, RX, SX, and DX as explainedbelow. The transfer transistor TX transfers photogenerated chargescollected by the photodiode PD to a floating diffusion region FD. Thereset transistor RX serves to set the potential of a node to a desiredvalue and discharge the photogenerated charges to reset the floatingdiffusion region FD.

The drive transistor DX serves as a source follower buffer amplifier.The select transistor SX performs addressing through a switchingoperation.

Here, the transfer transistor TX and the reset transistor RX include anative NMOS transistor, and the drive transistor DX and the selecttransistor SX include a normal NMOS transistor. The reset transistor RXis a transistor for correlated double sampling (CDS).

That is, in each image pixel of the CMOS image sensor, general CMOSelements are used to implement the photodiode and the transistors.Therefore, the existing CMOS process may be applied. Accordingly, anintegrated image signal processing and detecting unit may be provided ina block outside the pixel.

FIG. 1 is a cross-sectional view of a conventional CMOS image sensor.

Referring to FIG. 1, a punch-through prevention layer 12 is formed overa substrate 11. Furthermore, an epitaxially-grown silicon epitaxiallayer 13 is formed over the punch-through prevention layer 12. Anisolation layer 14 is formed from the surface of the silicon epitaxiallayer 13 to be separated from the punch-through prevention layer 12.

A gate dielectric layer 15A is formed over the silicon epitaxial layer13, a polysilicon layer 15B is formed over the gate dielectric layer15A, and a tungsten silicide layer 15C is formed over the polysiliconlayer 15B, thereby forming a gate electrode 15 of a transfer transistorTX. An N-type diffusion layer 16 is formed inside the silicon epitaxiallayer 13 while aligned with one edge of the gate electrode 15, and aP-type diffusion layer 17 is formed over the N-type diffusion layer 16and below the surface of the silicon epitaxial layer 13 while alignedwith the one edge of the gate electrode 15. As a result, a photodiode PDincluding the N-type diffusion layer 16 and the P-type diffusion layer17 is formed. Furthermore, a floating diffusion region 18 is formedinside the silicon epitaxial layer 13 while aligned with the other edgeof the gate electrode 15.

In the above-described conventional CMOS image sensor, when light isincident, the N-type diffusion layer 16, which serves as a depletionlayer, generates an electron hole pair (EHP). A hole h of the EHPescapes to the punch-through prevention layer 12, and an electron e isstored and then moved to the floating diffusion region 18 through thetransfer transistor TX. Then, the electron e is converted into imagedata.

The conventional CMOS image sensor has concerns regarding the occurrenceof dark current and decrease in photosensitivity. That is, when stronglight is irradiated from outside for a long time, the photogeneratedcharges of the photodiode PD are partially transferred to the floatingdiffusion region 18 through a channel of the gate electrode 15, therebycausing dark current. Accordingly, the photosensitivity decreases.

Here, a technique to apply a negative charge pumping (NCP) bias to thegate electrode 15 may be adopted to prevent the dark current and improvethe photosensitivity. In this case, a blooming phenomenon thatdeteriorates a trade-off characteristic may occur.

The blooming phenomenon includes pixel blooming and dark blooming. Inparticular, the dark blooming is a defect source that may cause a largeyield loss.

The blooming phenomenon occurs due to a channel blocking of a gateelectrode based on a barrier increase of the gate electrode caused bythe application of the NCP bias to the gate electrode. Furthermore, whena specific photodiode is fully charged under a high illuminationcondition during a specific integration time in the photodiode or undera dark condition caused by a large defect source of the photodiode,photogenerated charges may leak to adjacent pixels through the substratedue to the channel blocking of the gate electrode when the NCP bias isnot applied to the gate electrode.

SUMMARY

Exemplary embodiments of the present invention are directed to a CMOSimage sensor capable of suppressing a blooming phenomenon and crosstalk.

In accordance with an embodiment of the present invention, a CMOS imagesensor includes, a substrate, a gate electrode of a transfer transistorformed over the substrate, a photodiode formed over the substrate to besubstantially aligned with one side of the gate electrode, a floatingdiffusion region formed over the substrate to be substantially alignedwith the other side of the gate electrode, and a blooming pass regionformed below the photodiode.

In accordance with another embodiment of the present invention, a methodfor fabricating a CMOS image sensor includes forming a substrate,forming a blooming pass region over the substrate, forming a gateelectrode over the substrate so that the center of the gate electrode issubstantially aligned with one side of the blooming pass region, forminga photodiode over the blooming pass region so that the photodiode issubstantially aligned with one side of the gate electrode, and forming afloating diffusion region over the substrate so that the floatingdiffusion region is substantially aligned with the other side of thegate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional CMOS image sensor.

FIGS. 2A to 2C are diagrams for explaining a CMOS image sensor.

FIGS. 3A and 3B are energy band diagrams of a CMOS image sensorstructure.

FIG. 4 is a cross-sectional view of a CMOS image sensor in accordancewith a first embodiment of the present invention.

FIG. 5 is a cross-sectional view of a CMOS image sensor in accordancewith a second embodiment of the present invention.

FIGS. 6A to 6G are cross-sectional view illustrating a method forfabricating the CMOS image sensor in accordance with the firstembodiment of the present invention.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

The drawings are not necessarily to scale and in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When a first layer is referred to as being“on” a second layer or “on” a substrate, it not only refers to a casewhere the first layer is formed directly on the second layer or thesubstrate but also a case where a third layer exists between the firstlayer and the second layer or the substrate.

FIGS. 2A to 2C are diagrams for explaining a complementary metal-oxidesemiconductor (CMOS) image sensor.

In FIG. 2A, a top drawing illustrates a pixel when light is notirradiated because a negative charge pumping (NCP) bias is not appliedto a gate electrode (dark condition), and the pixel is completelysaturated by a photodiode leakage source at a specific pixel. In FIG.2B, a top drawing illustrates when the NCP bias is applied to the gateelectrode, showing dark blooming in which photogenerated charges leak toadjacent pixels through a substrate.

In FIGS. 2A and 2B, bottom drawings illustrate that photogeneratedcharges leak to adjacent pixels at a condition that the NCP bias isapplied to the gate electrode, after a green (G) pixel positioned in thecenter is saturated by light irradiation.

Referring to FIG. 2C, when the same amount of light is irradiated ontothe respective pixels and saturation current values based on chargesphotogenerated by the respective pixels are equal to each other, thepixels generally approach the saturation current values in order ofgreen (G), red (R), and blue (B) pixels due to a sensitivity difference.However, since the time required for the G pixel to approach thesaturation current value is shortened compared to the red or blue (R/B)pixels when the NCP bias is applied, the photogenerated charges maydiffuse to the R/B pixels adjacent to the G pixel after the G pixelapproaches the saturation current value. Then, sensitivity curves of theR/B pixels may be distorted.

FIGS. 3A and 3B are energy band diagrams of a CMOS image sensorstructure.

FIG. 3A is an energy band diagram of a general CMOS image sensorstructure, and FIG. 3B is an energy band diagram when an NCP bias isapplied to the general CMOS image sensor structure.

Referring to FIG. 3A, it can be seen that a conduction band (EC) 600 ofa photodiode PD is lower than a substrate PSUB, a conduction band 600 ofa transfer transistor TX is higher than the conduction band 600 of thephoto diode PD, and a conduction band 600 of a floating diffusion regionFD is lower than the photodiode PD.

Meanwhile, referring to FIG. 3B, it can be seen that a conduction band(EC) 700 of the substrate PSUB is higher than the conduction band of thephotodiode PD, the conduction band 700 of the transfer transistor TX ishigher than the conduction band 700 of the substrate PSUB, and theconduction band 700 of the floating diffusion region FD is lower thanthe potential of the photodiode PD.

That is, when the NCP bias is applied, the height of the conduction band700 of the transfer transistor TX increases by h1, and therebypreventing photogenerated charges of the photodiode from beingtransferred to the floating diffusion region through a gate electrode.Accordingly, it is possible to suppress an occurrence of a dark current.

However, when the conduction band 700 of the transfer transistor TXbecomes higher than the conduction band 700 of the substrate PSUB,blooming may occur. More specifically, when the photogenerated chargesare stored beyond the saturation of the photodiode due to irradiation oflight onto the photodiode, the photogenerated charges are not controlledbeyond the saturation of the photodiode PD when the gate electrode isturned off, but may leak to adjacent pixels through the substrate.

FIG. 4 is a cross-sectional view of a CMOS image sensor in accordancewith a first exemplary embodiment of the present invention.

Referring to FIG. 4, a punch-through prevention layer 32 is formed overa substrate 31. The punch-through prevention layer 32 is formed bydoping the substrate 31 with high-concentration P-type impurities. Asilicon epitaxial layer 33, which is epitaxially-grown, is formed overthe substrate 31 and the punch-through prevention layer 32. The channelstop region 34 is formed from the surface of the silicon epitaxial layer33 to be separated from the top of the punch-through prevention layer32.

A gate dielectric layer 36A is formed over the silicon epitaxial layer33, a polysilicon layer 36B is formed over the gate dielectric layer36A, and a tungsten silicide layer 36C is formed over the polysiliconlayer 36B, thereby forming a gate electrode 36 of a transfer transistorTX. An N-type diffusion layer 37 is formed so that one side is coupledwith one side of the isolation layer 35 inside the silicon epitaxiallayer 33, and the other side is substantially aligned with one edge ofthe gate electrode 36. A P-type diffusion layer 38 is formed over theN-type diffusion layer 37 and below the surface of the silicon epitaxiallayer 33 to be substantially aligned with the one edge of the gateelectrode 36.

As a result, a photodiode PD that includes the N-type diffusion layer 37and the P-type diffusion layer 38 is formed. Here, the structure inaccordance with the embodiment of the present invention includes ablooming pass region 39 formed below the photodiode PD in the siliconepitaxial layer 33 to suppress a blooming phenomenon, which occurs whenan NCP bias is applied. The blooming pass region 39 is formed below theN-type diffusion layer 37 to be substantially aligned with a center 100of the gate electrode 36. That is, one side of the blooming pass region39 overlaps the photodiode PD while the other side of the blooming passregion 39 overlaps a part of the gate electrode 36.

Furthermore, one side of the blooming pass region 39 contacts one sideof the isolation layer 35 while the other side of the blooming passregion 39 contacts one side of the channel stop region 34.

At this time, the blooming pass region 39 may be formed byion-implanting phosphorous (P) as a second conductive-type material withproper energy and dose conditions. For example, approximately 200 keV to400 keV of energy and approximately 1×10¹⁰ dose/cm² to 3×10¹¹ dose/cm²of dose condition may be used. Furthermore, because the ion implantationis performed at a high energy condition, the blooming pass region 39 maybe formed to such a depth to reach the punch-through prevention layer 32inside the silicon epitaxial layer 33, thereby reducing a distance h1(shown in FIG. 3B) between the blooming pass region 39 and thepunch-through prevention layer 32.

Here, the blooming pass region 39 has a higher impurity concentrationthan the channel stop region 34.

Furthermore, the floating diffusion region 40 doped with N-typeimpurities is formed to be substantially aligned with one side of thegate electrode 36, while the photodiode PD is substantially aligned withthe other side of the gate electrode 36.

In the above-described image sensor in accordance with the firstexemplary embodiment of the present invention, the blooming pass region39 is formed below the photodiode PD. The blooming pass region 39 isformed in the silicon epitaxial layer 33 to overlap a part of the gateelectrode 36. Accordingly, the blooming pass region 39 may suppress theoccurrence of dark current and blooming. More specifically, when thegate electrode 36 is turned off to apply the NCP bias, a specific pixelphotodiode PD may be fully charged under a high illumination conditionduring a specific integration time of the photodiode PD or under a darkcondition caused by a large defect source of the photodiode PD by achannel blocking of the gate electrode 36 based on a barrier increase ofthe gate electrode 36. In this case, photogenerated charges {circlearound (1)} and {circle around (2)} do not leak to adjacent pixels{circle around (3)} and {circle around (4)}, but are transferred to thefloating diffusion region 40 through the blooming pass region 39, whichis formed to transfer the leaking photogenerated charges {circle around(1)} and {circle around (2)} to the floating diffusion region 40.Furthermore, since the capacity of the photodiode PD is improved in sucha structure, a full depletion region at an on condition of the gateelectrode is expanded to the punch-through prevention layer 32.Accordingly, it is possible to improve the photosensitivity, crosstalk,and the saturation level of the pixel.

FIG. 5 is a cross-sectional view of a CMOS image sensor in accordancewith a second exemplary embodiment of the present invention.

Referring to FIG. 5, a punch-through prevention layer 42 is formed overa substrate 41. The punch-through prevention layer 42 is formed bydoping the substrate 41 with high-concentration P-type impurities. Asilicon epitaxial layer 43, which is epitaxially-grown, is formed overthe substrate 41 and the punch-through prevention layer 42. The channelstop region 44 is formed from the surface of the silicon epitaxial layer43 to be separated from the top of the punch-through prevention layer42.

A gate dielectric layer 46A is formed over the silicon epitaxial layer43, a polysilicon layer 46B is formed over the gate dielectric layer46A, and a tungsten silicide layer 46C is formed over the polysiliconlayer 46B, thereby forming a gate electrode 46 of a transfer transistorTX. An N-type diffusion layer 47 is formed to be coupled with one sideof the isolation layer 45 inside the silicon epitaxial layer 43, whilesubstantially aligned with one edge of the gate electrode 46. A P-typediffusion layer 48 is formed over the N-type diffusion layer 47 andbelow the surface of the silicon epitaxial layer 43 to be substantiallyaligned with the one edge of the gate electrode 46.

As a result, a photodiode PD that includes the N-type diffusion layer 47and the P-type diffusion layer 48 is formed.

Here, the structure in accordance with the embodiment of the presentinvention includes a blooming pass region 49 below the photodiode PD inthe silicon epitaxial layer 43 to suppress a blooming phenomenon, whichoccurs when an NCP bias is applied. The blooming pass region 49 isformed in a portion of the silicon epitaxial layer 43 below the N-typediffusion layer 47 to be substantially aligned with a center 200 of thegate electrode 46. In other words, one side of the blooming pass region49 overlaps a part of the photodiode PD while the other side of theblooming pass region 49 overlaps a part of the gate electrode 46.

Furthermore, one side of the blooming pass region 49 is spaced from oneside of the isolation layer 45 at a predetermined distance 202, whilethe other side surface of the blooming pass region 49 contacts the otherside of the channel stop region 44.

At this time, the blooming pass region 49 may be formed byion-implanting phosphorous (P) as a second conductive-type material atproper energy and dose conditions. For example, approximately 200 keV to400 keV of energy and approximately 1×10¹⁰ dose/cm² to 3×10¹¹ dose/cm²of dose condition may be used. Furthermore, because the ion implantationis performed at a high energy condition, the blooming pass region 49 maybe formed to such a depth to reach the punch-through prevention layer 42inside the silicon epitaxial layer 43, thereby reducing a distance h1(shown in FIG. 3B) between the blooming pass region 49 and thepunch-through prevention layer 42.

Here, the blooming pass region 49 has a higher impurity concentrationthan the channel stop region 44.

Furthermore, the floating diffusion region 50 doped with N-typeimpurities is formed to be substantially aligned with one side of thegate electrode 46, while the photodiode PD is substantially aligned withthe other side of the gate electrode 46.

In the above-described image sensor in accordance with the secondexemplary embodiment of the present invention, the blooming pass region49 is formed below the photodiode PD. The blooming pass region 49 isformed in the silicon epitaxial layer 43 so that one side of bloomingpass region 49 contacts the one side of the channel stop region 44 whilesubstantially aligned with the center 200. Accordingly, the bloomingpass region 49 may suppress the occurrence of blooming. Morespecifically, when the gate electrode 46 is turned off to apply the NCPbias, a specific pixel photodiode PD may be fully charged under a highillumination condition during a specific integration time of thephotodiode PD or under a dark condition caused by a large defect sourceof the photodiode PD by channel blocking of the gate electrode 46 basedon a barrier increase of the gate electrode 46. In this case,photogenerated charges {circle around (5)} and {circle around (6)} donot leak to adjacent pixels {circle around (7)} and {circle around (8)},but are transferred to the floating diffusion region 50 through theblooming pass region 46 that is formed to transfer the leakingphotogenerated charges {circle around (5)} and {circle around (6)} tothe floating diffusion region 50. Furthermore, since the capacity of thephotodiode PD is improved in such a structure, a full depletion regionat an on condition of the gate electrode 46 is expanded to thepunch-through prevention layer 42. Accordingly, it is possible toimprove the photosensitivity, crosstalk, and the saturation level of thepixel.

FIGS. 6A to 6G are cross-sectional view illustrating a method forfabricating the CMOS image sensor in accordance with the firstembodiment of the present invention.

Referring to FIG. 6A, a punch-through prevention layer 52 is formed overa substrate 51. The punch-through layer 52 may include an impurity layerformed by doping the substrate 51 with high-concentration P-typeimpurities.

The impurities for forming the punch-through prevention layer 52 mayinclude P-type impurities, for example, boron (B). The dopingconcentration of the impurities may be set to at least 1×10¹⁸ atoms/cm²,in order to secure the characteristics of the punch-through preventionlayer 52.

A silicon epitaxial layer 53 is formed over the substrate 51 and thepunch-through prevention layer 52. In the silicon epitaxial layer 53,components of the CMOS image sensor, such as a photodiode, are formed,and the silicon epitaxial layer 53 is formed to have a single-crystalstate. The silicon epitaxial layer 53 having a single-crystal state maybe formed, for example, by an epitaxial growth method.

The silicon epitaxial layer 53 may include a silicon epitaxial layerdoped with impurities. The impurities may have the same conductive type(P-type) as the punch-through prevention layer 52, and have a lowerdoping concentration than the punch-through prevention layer 52.

Here, the reason why the silicon epitaxial layer 53 is grown is asfollows. When the silicon epitaxial layer 53 exists, the depletion layerdepth of the photodiode PD may be increased to obtain a desirablephotosensitivity characteristic. Furthermore, a crosstalk between unitpixels, which is caused by irregular motions of electrons generated atdeep portions of the punch-through prevention layer 52 where thedepletion layer of the photodiode PD does not reach, may be prevented byrecombining the electrons through the punch-through prevention layer 52.

Referring to FIG. 6B, a channel stop region 54 may be formed, forexample, by ion-implanting low concentration P-type impurities into aportion of the silicon epitaxial layer 53 where an isolation layer is tobe formed.

Although not illustrated, the channel stop region 54 may be formed bythe following process. First, an ion implantation mask for forming thechannel stop region 54 is formed over the silicon epitaxial layer 53.Then, low concentration P-type impurities, for example, boron (B₁₁) areion-implanted into the exposed silicon epitaxial layer 53 using the ionimplantation mask, thereby forming the channel stop region 54. When theimpurities for forming the channel stop region 54 are ion-implanted, theimpurities may be implanted without a tilt, or be implanted whilerotated or twisted with a tilt.

An isolation layer 55 for isolating adjacent unit pixels is formed inthe silicon epitaxial layer 53.

Although not illustrated, an isolation mask is formed over the siliconepitaxial layer 53, to form the isolation layer 55. At this time, a maskprocess for forming the isolation mask may include a shallow trenchisolation (STI) process.

For example, pad oxide and pad nitride are sequentially deposited on thesilicon epitaxial layer 53, and photoresist is applied onto the padnitride. Then, a patterning process that includes exposure anddevelopment is performed to form the isolation mask for forming atrench.

The pad oxide and the pad nitride, which are exposed by the isolationmask, are simultaneously etched to partially expose the surface of thesilicon epitaxial layer 53. Then, the exposed silicon epitaxial layer 53is etched to a predetermined depth toward the punch-through preventionlayer 52, thereby forming a trench.

After the isolation mask is removed, oxide is deposited on the entiresurface of the resulting structure, including the trench, by chemicalvapor deposition (CVD) exhibiting a desirable gap-fill characteristic,and may be planarized by chemical mechanical polishing (CMP) until thepad nitride and the pad oxide are removed. The planarized oxide may beisotropically etched by wet etching to form the isolation layer 55buried in the trench.

Referring to FIG. 6C, a blooming pass region 57 is formed in the siliconepitaxial layer 53. The blooming pass region 57 collects electrons,which are not stored in the photodiode PD and are susceptible to leakageto other unit pixels.

The blooming pass region 57 may be formed by the following process.

First, photoresist is applied on the silicon epitaxial layer 53 and thenselectively patterned to form a first mask 56 for ion-implanting N-typeimpurities.

At this time, one side of the first mask 56 is substantially alignedwith one side of the channel stop region 54, and the other side of thefirst mask 56 is substantially aligned with a predetermined portion ofthe isolation layer 55, thereby exposing the surface of the siliconepitaxial layer 53 where the blooming pass region 57 is to be formed.

Using the first mask 56 as an ion implantation mask, N-type impuritiesare ion-implanted to form the blooming pass region 57 in the siliconepitaxial layer 53.

At this time, one side of the blooming pass region 57 contacts one sideof the isolation layer 55, and the other side surface of the bloomingpass region 57 contacts one side surface of the channel stop region 54.

The blooming pass region 57 may be formed by ion-implanting N-typeimpurities (P) into the silicon epitaxial layer 53 at proper energy anddose conditions. For example, approximately 200 keV to 400 keV of energyand approximately 1×10¹⁰ dose/cm² to 3×10¹¹ dose/cm² of dose conditionmay be used. Furthermore, because the ion implantation is performed at ahigh energy condition, the blooming pass region 57 may be formed to sucha depth to reach the punch-through prevention layer 52 inside thesilicon epitaxial layer 53, thereby reducing a distance h1 (shown inFIG. 3B) between the blooming pass region 57 and the punch-throughprevention layer 52.

The position and depth of the blooming pass region 57 may be controlledbased on the energy and dose conditions.

Referring to FIG. 6D, after the blooming pass region 57 is formed by theabove-described process, a gate dielectric layer 58A is formed over thesilicon epitaxial layer 53 so that one side of the blooming pass region57 is substantially aligned with the center of a subsequent gateelectrode. A polysilicon layer 58B, a tungsten silicide layer 58C, and asacrificial oxide layer 58D are sequentially deposited over the gatedielectric layer 58A.

The sacrificial oxide layer 58D, the tungsten silicide layer 58C, thepolysilicon layer 58B, and the gate dielectric layer 58A aresimultaneously patterned to form a gate electrode 58 of a transistor ofa unit pixel, for example, a transfer transistor.

At this time, the gate electrode 58 is formed in such a manner that thecenter 300 (shown in FIG. 6G) of the gate electrode is substantiallyaligned with one side surface of the blooming pass region 57.

Referring to FIG. 6E, photoresist is applied to the entire surface ofthe resulting structure including the sacrificial oxide layer 58D, andselectively patterned to form a second mask 59 for ion-implantinglow-concentration N-type impurities at a high energy condition.

At this time, one side of the second mask 59 is substantially alignedwith one side of the gate electrode including the sacrificial oxidelayer 58D, and the other side of the second mask 59 is substantiallyaligned with a predetermined portion of the isolation layer 55, therebyexposing the surface of the silicon epitaxial layer 53 where thephotodiode is to be formed.

Using the second mask 59 as an ion implantation mask, N-type impuritiesare ion-implanted to form an N-type diffusion layer 60 over the surfaceof the blooming pass region 57. At this time, one side of the N-typediffusion layer 60 is substantially aligned with one side of the gateelectrode 58, and the other side of the N-type diffusion layer 60contacts one side surface of the isolation layer 55.

Then, the second mask 59 is reused to form a P-type diffusion layer 61over the silicon epitaxial layer 53 exposed by the second mask 59, thatis, over the N-type diffusion layer 60 and below the surface of thesilicon epitaxial layer 53, such that the P-type diffusion layer 61 issubstantially aligned with the one side of the gate electrode 58.

Through the above-described ion implantation process of P-typeimpurities, a PN junction that includes the P-type diffusion layer 61and the N-type diffusion layer 60 is formed, and an expanded photodiodethat includes the silicon epitaxial layer 53, the blooming pass region57, the N-type diffusion layer 60, and the P-type diffusion layer 61 isformed.

Referring to FIG. 6F, the second mask 59 and the sacrificial layer 58Dare removed, and a photoresist is applied onto the entire surface of theresulting structure and patterned through exposure and development toform a third mask 62 exposing the channel stop region 54.

Using the third mask 62 as an ion implantation mask, N-type impuritiesare ion-implanted to form a floating diffusion region 63. Then, thethird mask 62 is removed to complete the CMOS sensor as illustrated inFIG. 6G.

In accordance with the embodiments of the present invention, theblooming pass region is formed below the photodiode, thereby suppressingblooming and crosstalk. Furthermore, it is possible to suppress bloomingand crosstalk, which occur when a negative charge pumping voltage isapplied to the gate electrode. In addition, as the capacitor area of thephotodiode is sufficiently secured, it is possible to improve thephotosensitivity.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

What is claimed is:
 1. A CMOS image sensor comprising: a substrate; agate electrode of a transfer transistor formed over the substrate; aphotodiode formed over the substrate to be substantially aligned withone side of the gate electrode; a floating diffusion region formed overthe substrate to be substantially aligned with the other side of thegate electrode; and a blooming pass region formed below the photodiode.2. The CMOS image sensor of claim 1, wherein one side of the bloomingpass region is substantially aligned with a center of the gateelectrode.
 3. The CMOS image sensor of claim 1, wherein one side of theblooming pass region overlaps the photodiode, and the other side of theblooming pass region overlaps a part of the gate electrode.
 4. The CMOSimage sensor of claim 1, wherein one side of the blooming pass regionoverlaps a part of the photodiode, and the other side of the bloomingpass region overlaps a part of the gate electrode.
 5. The CMOS imagesensor of claim 1, wherein the photodiode comprises a P-type diffusionlayer formed at the surface of the substrate and an N-type diffusionlayer formed below the P-type diffusion layer, and the blooming passregion contacts the N-type diffusion layer.
 6. The CMOS image sensor ofclaim 5, wherein the blooming pass region is doped with N-typeimpurities.
 7. The CMOS image sensor of claim 1, wherein the bloomingpass region contacts a bottom surface of the photodiode to collectphotogenerated charges which are not stored in the photodiode when thegate electrode is turned off to supply a negative charge pumpingvoltage.
 8. The CMOS image sensor of claim 1, further comprising: achannel stop region formed below the floating diffusion region.
 9. TheCMOS image sensor of claim 8, wherein the blooming pass region has ahigher impurity doping concentration than the channel stop region. 10.The CMOS image sensor of claim 8, wherein one side of the channel stopregion is substantially aligned with the center of the gate electrode tocontact the one side of the blooming pass region.
 11. A method forfabricating a CMOS image sensor, comprising: forming a substrate;forming a blooming pass region over the substrate; forming a gateelectrode over the substrate so that the center of the gate electrode issubstantially aligned with one side of the blooming pass region; forminga photodiode over the blooming pass region so that the photodiode issubstantially aligned with one side of the gate electrode; and forming afloating diffusion region over the substrate so that the floatingdiffusion region is substantially aligned with the other side of thegate electrode.
 12. The method of claim 11, further comprising: forminga channel stop region, before the formation of the blooming pass region,wherein the channel stop region contacts the floating diffusion region.13. The method of claim 11, wherein the blooming pass region is formedto overlap the entire surface of the photodiode and a part of the gateelectrode.
 14. The method of claim 11, wherein the blooming pass regionis formed to overlap a part of the photodiode and a part of the gateelectrode.
 15. The method of claim 11, wherein the blooming pass regionis formed by implanting N-type impurities.
 16. The method of claim 11,wherein the blooming pass region is formed by implanting phosphorous atenergy and dose conditions of approximately 200 keV to 400 keV andapproximately 1×10¹⁰ dose/cm² to 3×10¹¹ dose/cm², respectively.